1. Technical Field
The present invention relates to a method of fabricating a semiconductor device.
2. Related Art
Interconnect pitch has been becoming narrower with progress of dimensional shrinkage in recent semiconductor devices. In view of fabricating such leading-edge semiconductor devices, there is an increasing trend of using a multi-layered resist film composed of a plurality of resist films. In the multi-layered resist film, the upper resist film is first patterned by light exposure, and the resultant pattern is transferred to the lower film(s).
The conventional multi-layered resist film has been suffering from a problem in that the upper resist film is likely to cause collapse of pattern, as being affected by developer solution or rinse solution after the exposure. Japanese Laid-Open Patent Publication No. 2005-203563 describes a technique of forming a photosensitive film after cleaning the surface of a coating-type insulating film, followed by irradiation by an energy beam and development so as to form a photosensitive film pattern, thereby suppressing collapse/dropping of the photosensitive film pattern.
Another known problem is separation between a film-to-be-etched and the lower film thereof. Japanese Laid-Open Patent Publication No. 2002-093778 describes a technique by which a mask pattern composed of an oxide film such as SOG is formed on an organic film, an organic film which lies under the SOG film is etched through thus-patterned SOG film used as a mask, in a plasma of mixed gas of ammonia gas and oxygen gas. By this process, it is described that the separation at the interface between the oxide film and the organic film can be prevented, ensuring a highly accurate etched geometry.
Japanese Laid-Open Patent Publication No. 2006-53543 discloses a configuration in which the lower layer for the two-layered or three-layered resist process contains a polymer compound obtained by copolymerizing indenes with a compound containing a hydroxyl group or epoxy group together with a polymerizable double bond. This configuration reportedly has an excellent resistance against etching.
Japanese Laid-Open Patent Publication No. 2002-270584 describes a technique of the multi-layered resist process in which a fluorine component is added to an etching gas used for etching the lower resist film through a patterned intermediate layer used as a mask. The publication describes that the thickness of the lower film in the multi-layered film was successfully reduced to as thin as 250 nm or around.
Japanese Laid-Open Patent Publication No. 2004-47511 describes a technique of removing, using an inert gas plasma, residual electric charge of a wafer adsorbed to an electrostatic chuck by applying, to the chuck electrode, a charge removing voltage equivalent to the self-bias potential of the wafer during the plasma application. This configuration allows rapid and stable release of an object adsorbed onto the electrostatic chuck.
Japanese Laid-Open Patent Publication No. 2004-281832 describes a technique of loading/unloading a semiconductor substrate to or from the chambers of a semiconductor process apparatus, in which the semiconductor substrate is loaded/unloaded between each process chamber and a common transfer chamber, only when the pressure in each of the process chambers becomes lower than that of the common transfer chamber.
The present inventors found out that sometimes the lower film of the multi-layered resist also collapsed depending on conditions. Unlike the upper resist film, the lower resist film is patterned by dry etching. Because the lower resist film is not affected by a developer solution unlike the upper resist film, pattern collapse thereof has not conventionally been recognized as a problem. For this reason, there has been no technique ever developed for suppressing collapse of the lower resist film pattern.